This disclosure relates to data processing and storage, and more specifically, to techniques for storage command processing in a data storage system, such as a flash memory system.
NAND flash memory is an electrically programmable and erasable non-volatile memory technology that stores one or more bits of data per memory cell as a charge on the floating gate of a transistor or a similar charge trap structure. In a typical implementation, a NAND flash memory array is organized in blocks (also referred to as “erase blocks”) of physical memory, each of which includes multiple physical pages each in turn containing a multiplicity of memory cells. By virtue of the arrangement of the word and bit lines utilized to access memory cells, flash memory arrays can generally be programmed on a page basis, but are erased on a block basis.
As is known in the art, blocks of NAND flash memory must be erased prior to being programmed with new data. A block of NAND flash memory cells is erased by applying a high positive erase voltage pulse to the p-well bulk area of the selected block and by biasing to ground all of the word lines of the memory cells to be erased. Application of the erase pulse promotes tunneling of electrons off of the floating gates of the memory cells biased to ground to give them a net positive charge and thus transition the voltage thresholds of the memory cells toward the erased state. Each erase pulse is generally followed by an erase verify operation that reads the erase block to determine whether the erase operation was successful, for example, by verifying that less than a threshold number of memory cells in the erase block have been unsuccessfully erased. In general, erase pulses continue to be applied to the erase block until the erase verify operation succeeds or until a predetermined number of erase pulses have been used (i.e., the erase pulse budget is exhausted).
A NAND flash memory cell can be programmed by applying a positive high program voltage to the word line of the memory cell to be programmed and by applying an intermediate pass voltage to the memory cells in the same string in which programming is to be inhibited. Application of the program voltage causes tunneling of electrons onto the floating gate to change its state from an initial erased state to a programmed state having a net negative charge. Following programming, the programmed page is typically read in a read verify operation to ensure that the program operation was successful, for example, by verifying that less than a threshold number of memory cells in the programmed page contain bit errors. In general, program and read verify operations are applied to the page until the read verify operation succeeds or until a predetermined number of programming pulses have been used (i.e., the program pulse budget is exhausted).
Small Computer System Interface (SCSI) defines a set of standards for physically connecting and transferring data between computers and peripheral devices. Conventionally, SCSI has commonly been used for hard disk drives and tape drives. Today, SCSI is also used for flash memory based data storage systems. The SCSI standard defines command sets for specific peripheral device types. The SCSI command architecture was originally defined for parallel SCSI buses, but has been adapted with minimal change for use with Internet SCSI (iSCSI) and serial SCSI. In SCSI terminology, communication takes place between an initiator and a target. An initiator sends a command to a target, which responds in some manner to the command.
SCSI commands are sent in a command descriptor block (CDB) that includes a one byte operation code followed by five or more bytes that include command-specific parameters. At the end of a command sequence, a target returns a status code byte, such as 00h for success, 02h for an error, or 08h for busy. There are four categories of SCSI commands: N (non-data), W (writing data from initiator to target), R (reading data), and B (bidirectional). Among other commands, SCSI commands include: a read command, which causes data to be read from a target device; and a write command, which causes data to be written to a target device. Each device on a SCSI bus is assigned a unique SCSI identifier (ID). Devices may encompass multiple logical units that are addressed by logical unit number (LUN). Simple devices have just one LUN, more complex devices may have multiple LUNs.
SCSI command tag queuing refers to queuing multiple commands to a SCSI device. Queuing commands to a SCSI device can improve performance as it allows the SCSI device itself to determine the most efficient way to order and process commands. SCSI devices that support command tag queuing can be divided into two classes: devices that clear their queues on error and devices that do not. Devices that do not clear their queues on error resume processing of queued commands when the error condition is cleared, typically by receiving the next command. Devices that clear their queues flush all commands currently outstanding. Command tag queueing requires a SCSI adapter, a SCSI device, a SCSI device driver, and a SCSI adapter driver to support the capability. For a SCSI device driver to queue multiple commands to a SCSI device (that supports command tag queuing), the SCSI device driver is generally required to indicate whether each command is a simple command, a head of queue (HOQ) command, or an ordered command.